Noise Optimization of Readout Front Ends in CMOS Technology with PS Circuit


  • Wembe Tafo Evariste University of Douala, Cameroon
  • Moukengue Imano Adolphe University of Douala, Cameroon
  • Teko Daniel University of Douala, Cameroon
  • Djamet Yimga Arnaud University of Yaoundé I


Charge sensitive preamplifier, Noise, Pulse shaper, Moderate inversion, EKV model


In this paper, the study of the noise optimization of the charge sensitive preamplifier (CSP) for silicon strip, Si(Li), CdZnTe and CsI detectors is presented. The power limitation in such systems is available while a good noise performance and a fast signal processing time are required. This paper describes the CSP noise for CMOS technology with a chosen detector capacitance 3pF and transistor gate length ranging from 0.13 μm to 2μm. In this paper the designed CSP, followed by a fast pulse shaper (PS) stage, the equivalent noise charge (ENC) obtained is dominated by the thermal noise of an input MOS transistor. Noise behavior is evaluated with the input transistor works in a moderate inversion region. These analyses are made using a simplified EKV (Enz, Krummenacher, Vittoz) model and MATLAB simulations using BSIM3v3 models. We show several novel aspects of the noise optimization of the CSP regarding the optimum transistor width and the optimum of the drain current, and the sensitivity of the ENC between this width and the drain current.


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How to Cite

Evariste, W. T., Adolphe, M. I., Daniel, T., & Arnaud, D. Y. (2014). Noise Optimization of Readout Front Ends in CMOS Technology with PS Circuit. Asian Journal of Applied Sciences, 2(5). Retrieved from