Design and Simulation of a New Front-end Read-out Circuit based on Switched Capacitor Array (SCA)

Authors

  • Wembe Tafo Evariste University of Douala, Cameroon
  • Moukengue Imano Adolphe University of Douala, Cameroon
  • HU Hong Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China

Keywords:

Switched capacitor array, Sample and hold, Transient recorder, Transient digitizer, leakage current

Abstract

In this paper, a switched capacitor array (SCA) for front-end read-out circuit of silicon strip, Si(Li), CdZnTe and CsI detectors, etc., which has 7 channels and 448 sample/hold cells with up to 2 MHz sample rates, is designed. The circuit is completely made by CMOS technology and 64 switched capacitors per channel are used to record 7 parallel analog transient signals. Trigger and clock are provided by the combination of several counter rings with a number of logic chips. The readout is made in column and permits to read the entire channel at more than 32MHz rate. This paper will also describe a novel T-Network configuration which is used to eliminate leakage current in the reset switch for each integrator, and a Clock generator which is used to optimize the gate logic to ensure nonlinearity of the SCA less than 0.2% at the 2MHz sample rate.

References

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Published

2014-12-15

How to Cite

Evariste, W. T., Adolphe, M. I., & Hong, H. (2014). Design and Simulation of a New Front-end Read-out Circuit based on Switched Capacitor Array (SCA). Asian Journal of Applied Sciences, 2(6). Retrieved from https://www.ajouronline.com/index.php/AJAS/article/view/1916